Memory devices are widely used in a variety of digital electronics. One type of memory device is a dynamic random access memory (DRAM) device. DRAM devices can be used to form low cost high density memory arrays. For example, one of the largest applications for DRAM is as the main memory in modern computers. Unfortunately, due to the dynamic nature of its configuration, the information stored in DRAM will eventually degrade unless periodic memory refresh cycles are performed. Thus, though DRAM memory cells may be small in size, they may also consume large amounts of power due to the refresh requirements.
Another type of memory device is a non-volatile memory (NVM) device that has long data retention without the use of refresh cycles. This memory may also be referred to as static memory. In contrast to DRAM, NVM memory devices maybe more expensive but consume less power. Some examples of non-volatile memory include read-only memory (ROM) and Flash memory.
System designers therefore need to select the appropriate memory type for the systems they are designing. This means accounting for the trade-offs between size, cost, speed, power consumption, and volatility of the different memory types. In some cases, more resources (e.g., size and cost) are allocated for memory where multiple types of memory are needed to obtain the desired memory characteristics.
FIG. 1 shows a cross-section view of a conventional 3D NAND cell string 100 for use in a flash memory array. The cell string 100 includes a metal bit line 101 and a polysilicon or silicon channel 102. The cell string 100 also includes source 103 and drain 104 regions that may have the opposite types of doping. A silicon source line 105, a drain select gate (DSG) 106 and source select gate (SSG) 107 are also included. Memory cells are formed where word lines (WL0-WLn) (e.g., 108 and 109) intersect with a charge-trapping layer. For example, the cell string 100 also includes a gate oxide layer 110 and a charge-trapping layer 111, such as an Oxide-Nitride-Oxide (ONO) layer that traps electric charge to represent the cell's data. FIG. 2 shows a circuit representation of the 3D NAND cell string 100.
One significant drawback of conventional 3D NAND array structures that utilize the architecture of the cell string 100 is that of “program-disturb.” During programming, a selected word line (e.g., WL0) is supplied with a high voltage, such as +10V to +20V. All the unselected word lines (e.g., WL1-WLn) are supplied with a medium high voltage, such as +5V to +10V. This will boost the channel 102 of the cells to about +5V to +10V to program-inhibit the cell. However, this condition will cause significant program-disturb to some or all of the cells associated with the unselected word lines.
Furthermore, as the density of the 3D NAND array is increased, more word line layers will be stacked in one string, and thus the problem of program-disturb is increased. This problem will become even more severe for Multi-Level Cell (MLC) configurations because each level has a narrower voltage threshold (Vt) window.
Thus, the program-disturb problem has become a technical challenge for increasing the density of 3D NAND memory. It is therefore desirable to have a mechanism that overcomes the problem of program-disturb associated with convention memory arrays.